1. Field of the Invention
The invention relates generally to address generation systems in digital computers and specifically to a system for generating an address relative to an existing address.
2. Description of the Prior Art
Generally, a jump or branch instruction requires the provision of a target address to access the next instruction in a program sequence. Two existing addressing techniques are described in the literature. The first is absolute addressing in which the target address is usually fully specified within the literal (LIT) field of an instruction. The second is relative addressing in which the literal is taken as on offset from the current PC address.
Absolute addressing causes one of two problems depending upon the implementation. As it is generally used, it must allow for the embedded LIT field to be the same size as the target address (k+1 bits) for a 2.sup.k bit memory. This is very costly since it wastes memory locations to store these bits, and memory bandwidth to load the instruction along with the fully specified address. If absolute addresses are used with a LIT field that is smaller than the k+1 bits of total address than absolute addressing cannot guarantee both positive and negative offsets in the addressing range independent of the PC.
Relative branching reduces the size of LIT encoding, and takes advantage of the fact that most addresses can be arranged to be within a small range around the value of the PC. For a (j+1) bit LIT field, the relative address range is usually from +2.sup.j -1 to -2.sup.j. Additionally, a full k+1 bit adder is required to add the LIT field to PC, thereby imposing additional hardware and timing delay requirements on the system.
Both Absolute and Relative Addressing have been used on many computer systems.
Accordingly, a need exists for a system that guarantees positive and negative offsets from any PC value without wasting memory bandwidth and requiring excessive hardware and time delays.